1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to methods for fabricating transistor devices having a reduced pitch.
2. Description of Related Art
Modern integrated circuits contain numerous structures that comprise conductive material, semi-conductive material (i.e., rendered conductive in defined areas with dopants), and/or non-conductive material. For example, transistor devices are commonly fabricated by forming a semi-conductive material, such as polycrystalline silicon (polysilicon) over a relatively thin gate dielectric arranged upon a semiconductor substrate. The polysilicon material is patterned to define gate conductors spaced laterally apart above the substrate. Along with the gate conductors, exposed regions of the substrate are implanted with impurity dopants to form source/drain junctions in the substrate between the gate conductors. If the dopant species employed for forming the source/drain regions is n-type, then an NMOSFET (n-channel) transistor device is formed. Conversely, if the source/drain dopant species is p-type, then a PMOSFET (p-channel) transistor device is formed. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
Transistor gate conductors are defined using a technique known as photolithography. A photosensitive film, i.e., photoresist, is spin-deposited across the polysilicon material. An optical image is transferred to the photoresist by projecting a form of radiation, typically ultraviolet light, through the transparent portions of a mask plate. A photochemical reaction alters the solubility of the regions of the photoresist exposed to the radiation. The photoresist is washed with a solvent known as developer to preferentially remove the regions of higher solubility, followed by curing the remaining regions of the photoresist. Those remaining regions of the photoresist are highly resistant to attack by an etching agent that is capable of removing the polysilicon material. The portions of the polysilicon left exposed by the photoresist are etched away to define gate conductors of ensuing transistor devices.
Unfortunately, the minimum lateral dimension that can be achieved for a patterned photoresist feature is limited by, among other things, the resolution of the optical system used to project the image onto the photoresist. The term xe2x80x9cresolutionxe2x80x9d describes the ability of an optical system to distinguish closely spaced objects. Diffraction effects may undesirably occur as the radiation passes through slit-like transparent regions of the mask plate, scattering the radiation and therefore adversely affecting the resolution of the optical system. As such, the photoresist regions exposed to the radiation fail to correspond to the mask plate pattern, resulting in the photoresist features being skewed. Consequently, the photolithography process limits the minimum achievable widths of the features of a conventional integrated circuit. It is therefore difficult to reduce the widths of and distances between for example transistor gate conductors, which are defined by the photolithography process.
Because of this limitation of the photolithography process, the pitch of for example transistor devices formed with conventional methods cannot be easily reduced. The xe2x80x9cpitchxe2x80x9d is herein defined as the distance between the same points of two adjacent structures of the same type, e.g., two adjacent gate conductors. Since the pitch of the devices cannot be easily reduced, the device integration cannot be increased to meet the high demand for smaller and faster integrated circuits.
A need thus exists in the prior art to reduce the pitch of transistor devices of an integrated circuit. A further need exists to develop a method for fabricating an integrated circuit in which the width of and distances between the gate conductors are not limited by the photolithography process.
The present invention addresses these needs by providing a method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices, by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits.
In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer. The second polymer layer is used as an etching mask to define the conductive layer. Then, the second polymer layer is removed.
According to one aspect of the invention, transistors are formed using several process steps. A first conductive layer, a stop layer, and a second conductive layer are consecutively deposited on a semiconductor substrate. The first and second conductive layers may be composed of a conductive or semi-conductive material and are preferably composed of polysilicon. The stop layer may be a dielectric material having an etch rate less than an etch rate of the second conductive layer when using an etching agent (i.e., etchant) that is highly selective to the second conductive layer. If, for example, the conductive layers comprise polysilicon, the stop layer may be silicon nitride or silicon oxy-nitride. Subsequently, a photoresist layer is patterned on the second conductive layer using the photolithography process. A first dielectric layer is then selectively formed on surfaces of the photoresist layer. The first dielectric layer may be composed of a polymer created in an etcher using the dielectric resolution enhancement coating technique. The first conductive layer, the stop layer, and the second conductive layer are defined using the first dielectric layer as an etching mask. Having served their purpose, the photoresist layer and the first dielectric layer are then removed.
Next, an insulating layer is deposited on the substrate to a level above the second conductive layer. The insulating layer may be composed of an oxide, e.g., a spin on glass (SOG) oxide, such that its etch rate is less than the etch rate of the second conductive layer when an etchant that is highly selective to the second conductive layer is used. The insulating layer is then removed down to the upper surface of the second conductive layer, thereby exposing the second conductive layer. A dry etching process or a chemical-mechanical polishing (CMP) process may be employed to remove the insulating layer. The second conductive layer is then removed to expose the stop layer, followed by forming a second dielectric layer, e.g., a polymer, on surfaces of the insulating layer to serve as an etch mask. The dielectric resolution enhancement coating technique, which can be performed in an etcher, may be used to form the second dielectric layer. Subsequently, portions of the stop layer and first conductive layer not covered by the second dielectric layer may be removed.
The second dielectric layer is removed, leaving behind a plurality of gate conductors that are laterally spaced apart on a substrate, and an etch stop material positioned over the gate conductors. A gate dielectric is interposed between the substrate and the plurality of gate conductors. Transistor devices may be subsequently formed by implanting dopants into source/drain regions of the substrate located between the gate conductors. A lateral width of each gate conductor is substantially less than a lateral width of a feature of a conventional, patterned photoresist layer. Moreover, a pitch of the plurality of gate conductors is substantially less than a pitch of features of a conventional, patterned photoresist layer. The resulting pitch of the transistor devices fabricated according to this method is significantly reduced compared to the pitch of conventional transistor devices.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.